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general description the max7469/MAX7470 triple-channel, anti-aliasing fil- ters and buffers are ideal for high-definition (hd) and standard-definition (sd) television (tv) applications. compatible with 1080i, 720p, 720i, 480p, and 480i scanning system standards and computer format sig- nals, the max7469/MAX7470 support component video (y p b p r , g s br, and rgbhv), as well as composite (cvbs) and s-video (y/c). the max7469/MAX7470 limit the input bandwidth for anti-aliasing and out-of-band noise reduction prior to digital conversion by an adc or video decoder. the max7469/MAX7470 frequency response can be contin- uously varied in 256 linear steps through an i 2 c* inter- face from below sd resolution to beyond hd resolution. the output buffers of the max7469/MAX7470 drive a 2v p-p video signal into a standard 150 load. the inputs are ac-coupled, and the outputs can be either dc- or ac-coupled. the max7469 has a gain of 0db, and the MAX7470 has a gain of +6db. both devices are available in a 20-pin tqfn package and are fully specified over the 0? to +85? upper-commercial temperature range. applications hdtv (lcd, pdp, dlp, crt) set-top boxes personal video recorders home theaters features continuously variable anti-aliasing filter 5mhz to 34mhz in 256 steps supports all standard video and computer input formats 480i, 480p, 720i, 720p, 1080i qvga, vga, svga, xga, sxga, uxga y p b p r , g s br, rgbhv, y/c, cvbs accepts any input sync format sync on y, sync on g, external sync (positive or negative) sync on all channels buffered outputs drive standard 150 video load 0db (max7469) +6db (MAX7470) dc- or ac-coupled outputs single +5v analog and +3.3v digital supplies 5mw power-down mode 20-pin tqfn lead-free package max7469/MAX7470 part pin-package buffer gain (db) pkg code m a x7 4 6 9 u tp + 20 tqfn-ep* 0 t2055-4 m a x7 4 7 0 u tp + ** 20 tqfn-ep* +6 t2055-4 ordering information 19-0548; rev 0; 5/06 hdtv continuously variable anti-aliasing filters typical operating circuit appears at end of data sheet. * purchase of i 2 c components from maxim integrated products, inc., or one of its sublicensed associate companies, conveys a license under the philips i 2 c patent rights to use these compo- nents in an i 2 c system, provided that the system conforms to the i 2 c standard specification defined by philips. ________________________________________________________________ maxim integrated products 1 for pricing delivery, and ordering information please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. note: all devices are specified over the 0? to +85? operating temperature range. + indicates lead-free packaging. * ep = exposed pad. ** future product?ontact factory for availability. pin configuration max7469 MAX7470 tqfn (5mm x 5mm) *exposed pad. see pin description for connection. top view 19 20 18 17 7 6 8 extsync sda dv dd 9 dgnd gnd a0 av dd gnd 12 in2 45 15 14 12 11 gnd in3 av dd out2 av dd out3 scl a1 3 13 gnd 16 10 out1 in1 + *ep
max7469/MAX7470 hdtv continuously variable anti-aliasing filters 2 ________________________________________________________________________________________ av dd to gnd............................................................-0.3v to +6v dv dd to dgnd.........................................................-0.3v to +4v in_, extsync to gnd ................................................................. ..................................-0.3v to the lower of (av dd + 3v) and +6v out_ to gnd ............................................................................... ..................................-0.3v to the lower of (av dd + 3v) and +6v a_ to gnd .................................................................................... ..................................-0.3v to the lower of (av dd + 3v) and +6v scl, sda to dgnd ..................................................-0.3v to +6v continuous power dissipation (t a = +70?) 20-pin tqfn (derate 33.3mw/? above +70?) ...2666.7mw maximum current into in_, a_, gnd, scl, sda, and extsync............................................?0ma operating temperature range...............................0? to +85? storage temperature range .............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? absolute maximum ratings electrical characteristics (av dd = +5v ?%, dv dd = 2.7v to 3.6v, r load = 150 to gnd, c in = 0.1?, t a = 0? to +85?, unless otherwise noted. typical values are at av dd = 5v, dv dd = 3.3v, t a = +25?.) parameter symbol conditions min typ max units hd: f = 100khz to 30mhz, relative to 100khz (note 1) -3 -0.6 +1 filter passband response a pb sd: f = 100khz to 5.75mhz, relative to 100khz (note 2) ?.1 ?.0 db hd: f = 74mhz (note 1) 45 57 filter stopband attenuation a sb sd: f = 27mhz (note 2) 52 63 db hd: 100khz to 30mhz, relative to 100khz (note 1) 20 group delay deviation t g sd: 100khz to 5.75mhz, relative to 100khz (note 2) 15 ns hd: channel to channel, 100khz to 2mhz, (note 1) 5 group delay matching t g ( match ) sd: channel to channel, 100khz to 500khz, (note 2) 1.5 ns bypass frequency response -3db, bypass mode, independent of filter setting 100 mhz sd differential gain dg five-step modulated staircase (note 2) 0.25 % sd differential phase d five-step modulated staircase (note 2) 0.25 degrees signal-to-noise ratio snr output signal (2v p-p ) to rms noise (100khz to 30mhz), f = 30mhz 69 db sd line-time distortion h dist deviations in a line with an 18?, 100 ire bar; 1 line = 63.5? (note 2) 0.3 % sd field-time distortion v dist deviations in 130 lines with 18?, 100 ire bars (note 2) 0.3 % stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
max7469/MAX7470 hdtv continuously variable anti-aliasing filters _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = +5v ?%, dv dd = 2.7v to 3.6v, r load = 150 to gnd, c in = 0.1?, t a = 0? to +85?, unless otherwise noted. typical values are at av dd = 5v, dv dd = 3.3v, t a = +25?.) parameter symbol conditions min typ max units positive 350 clamp settling time to 1% with 100 ire step (note 4) negative 650 h minimum functional input sync amplitude 125 mv max7469 -0.5 0 +0.5 low-frequency gain (note 1) MAX7470 5.5 6 6.5 db low-frequency gain matching 100khz 0.05 db maximum output voltage amplitude dc to 30mhz 2.4 v p-p max7469 2.4 maximum input voltage amplitude MAX7470 1.2 v p-p channel-to-channel isolation 62 db output clamping level variation (notes 1, 4) ?00 mv power-supply rejection ratio psrr dc 50 db digital inputs (extsync, a1, a0) input logic-high voltage v ih 2.0 v input logic-low voltage v il 0.8 v input leakage current i in v in = 0 to dv dd ? ?0 ? input capacitance c in 6pf digital inputs (sda, scl) input logic-high voltage v ih 0.7 x dv dd v input logic-low voltage v il 0.3 x dv dd v input hysteresis v hyst 0.05 x dv dd v input leakage current i in v in = 0 to dv dd ?.1 ?0 ? input capacitance c in 6pf digital output (sda) output logic-low voltage v ol i sink = 3ma 0.4 v tri-state leakage current i l v in = 0 to dv dd ?.1 ?0 ? tri-state output capacitance c out 6pf power requirements analog supply voltage range av dd 4.75 5 5.25 v digital supply voltage range dv dd 2.7 3.3 3.6 v normal operation, no load 180 200 analog supply current i avdd power-down mode, no load 1 1.5 ma digital supply current i dvdd f scl = 400khz 25 ?
max7469/MAX7470 hdtv continuously variable anti-aliasing filters 4 ________________________________________________________________________________________ timing characteristics parameter symbol conditions min typ max units serial-clock frequency f scl 0 400 khz bus free time between stop (p) and start (s) condition t buf 1.3 ? hold time (repeated) start (sr) condition t hd ; sta after this period, the first clock pulse is generated 0.6 ? scl pulse-width low t low 1.3 ? scl pulse-width high t high 0.6 ? setup time for a repeated start (sr) condition t su;sta 0.6 ? data hold time t hd ; dat (note 5) 0.0 0.9 ? data setup time t su ; dat 100 ns rise time of both sda and scl signals, receiving t r 0 300 ns fall time of both sda and scl signals, receiving t f 0 300 ns fall time of sda signal, transmitting t f (note 6) 20 + 0.1c b 250 ns setup time for stop (p) condition t su ; sto 0.6 ? capacitive load for each bus line c b 400 pf pulse width of spikes that are suppressed by the input filter t sp (note 7) 0 50 ns (av dd = +5v ?%, dv dd = 2.7v to 3.6v, r load = 150 to gnd, c in = 0.1?, t a = 0? to +85?, unless otherwise noted. typical values are at av dd = 5v, dv dd = 3.3v, t a = +25?.) note 1: the filter passband edge is set to code 255. note 2: the filter passband edge is set to code 40. note 3: 1h is the total line period, depending on the video standard. for ntsc, this is 63.5?; for hdtv, the line period is 29.64?. note 4: the clamp level is at the sync tip for signals with sync pulses, and at the blanking level otherwise. note 5: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of the scl signal) to bridge the undefined region of scl? falling edge. note 6: c b = total capacitance of one bus line in pf. t r and t f measured between 0.3v dd and 0.7v dd . note 7: input filters on the sda and scl inputs suppress noise spikes less than 50ns.
max7469/MAX7470 hdtv continuously variable anti-aliasing filters _______________________________________________________________________________________ 5 sda scl t f t r t f s r t hd;sta t hd;dat t high t su;dat t su;sta t hd;sta t su;sto t sp t r s s p t low t sp figure 1. 2-wire, serial-interface timing diagram (av dd = +5v, dv dd = 3.3v, r load = 150 to gnd, c load = 0 to 20pf to gnd, c in = 0.1?, t a = +25?, unless otherwise noted.) typical operating characteristics -80 -60 -70 -30 -40 -50 0 -10 -20 10 0.1 10 1 100 1000 frequency response (max7469) max7469 toc01 frequency (mhz) response (db) code 40 code 90 code 220 code 255 -1.5 -2.0 -2.5 -3.0 -1.0 0 -0.5 0.5 1.0 0.1 10 1100 passband flatness (max7469) max7469 toc02 frequency (mhz) response (db) code 40 code 255 code 220 code 90 -40 -50 -60 -70 -30 -10 -20 0 10 0.1 10 1 100 1000 frequency response (MAX7470) max7469 toc03 frequency (mhz) response (db) code 40 code 90 code 220 code 255 4.5 4.0 3.5 3.0 5.0 6.0 5.5 6.5 7.0 0.1 10 1 100 passband flatness (MAX7470) max7469 toc04 frequency (mhz) response (db) code 40 code 255 code 220 code 90 40 30 20 10 0 50 70 60 80 90 0.1 1 10 100 group delay max7469 toc05 frequency (mhz) delay (ns) sd hd 200ns/div 2t response (1 ire = 7.14mv) 300mv/div max7469 toc06 300mv/div
max7469/MAX7470 hdtv continuously variable anti-aliasing filters 6 ________________________________________________________________________________________ (av dd = +5v, dv dd = 3.3v, r load = 150 to gnd, c load = 0 to 20pf to gnd, c in = 0.1?, t a = +25?, unless otherwise noted.) typical operating characteristics (continued) 400ns/div modulated 12.5t response (1 ire = 7.14mv) 300mv/div max7469 toc07 300mv/div differential gain max7469 toc08 differential phase (deg) 13 245 6 7 13 245 6 7 0.1 0.2 0 -0.1 -0.2 0.1 0.2 0 -0.1 -0.2 differential gain (%) differential phase -3db frequency vs. control code max7469 toc09 code measured -3db frequency (mhz) 204 153 102 51 6 12 18 24 30 36 0 0255 -40 -10 -15 -20 -25 -30 -35 0 -5 5 10 0.1 10 1 100 1000 bypass-mode frequency response max7469 toc10 frequency (mhz) response (db) MAX7470 max7469 0 4 12 8 16 20 0.1 10 1 100 bypass-mode group delay max7469 toc11 frequency (mhz) delay (ns)
max7469/MAX7470 detailed description the max7469/MAX7470 are complete video anti-alias- ing solutions, ideal for fixed-pixel hdtv display tech- nologies, such as plasma and lcd, which digitize the input video signal and then scale the resolution to match the native pixel format of the display. with a soft- ware-selectable corner frequency ranging from 5mhz to 34mhz, the max7469/MAX7470 support both sd and hd video signals, including 1080i, 720p, 720i, 480p, and 480i. higher bandwidth computer resolution signals are also supported. integrated lowpass filters limit the analog video input bandwidth for anti-aliasing and out-of-band noise reduction prior to sampling by an adc or video decoder. by allowing the corner frequency to be adjust- ed from below sd resolution to beyond hd resolutions in 256 linear steps, the filter? corner frequency can be optimized dynamically for a specific input video signal and the sampling frequency of the adc or video decoder. for applications requiring a passband greater than the maximum frequency setting, a filter bypass mode is also provided. an i 2 c interface allows a microcontroller (?) to config- ure the max7469/MAX7470s?performance and func- tionality, including the clamp voltage, the filter corner frequency, the sync source (internal/external), filter bypassing, etc. the typical operating circuit shows the max7469/ MAX7470 block diagram and typical external connections. sync detector and clamp settings the max7469/MAX7470 use a video clamp circuit to establish a dc offset for the incoming video signal after the ac-coupling capacitor. this video clamp sets the dc bias level of the circuit at the optimum operating point. the max7469/MAX7470 support both internal and external sync detection. selection of internal vs. external detection is achieved by programming the command byte (see table 3). after extracting the sync information from channel 1 (or an external sync: synca, syncb, or sync), the max7469/MAX7470 clamp the video signal during the sync tip portion of the video. select one of two possible clamp levels according to the input signal format. use the low level when the input signal contains sync information, such as a y (luma) or cvbs signal. pin description pin name function 1 dgnd digital ground. see the power-supply bypassing and layout considerations section. 2 extsync e xter nal s ync inp ut. e x ts y n c has an i nter nal 3m r esi stor to g r ound . c onnect to g r ound i f not used . 3 scl i 2 c-compatible serial-clock input 4 sda i 2 c-compatible serial-data input/output 5dv dd digital power supply. bypass to dgnd with a 0.1? capacitor. see the power-supply bypassing and layout considerations section. 6 out3 video output 3. out3 can be either dc- or ac-coupled. 7, 9, 11 av dd analog power supply. bypass to gnd with a 0.1? capacitor. see the power-supply bypassing and layout considerations section. 8 out2 video output 2. out2 can be either dc- or ac-coupled. 10 out1 video output 1. out1 can be either dc- or ac-coupled. 12 a0 i 2 c device address bit 0 13 a1 i 2 c device address bit 1 14, 15, 17, 19 gnd ground. connect all gnd pins to the ground plane. see the power-supply bypassing and layout considerations section. 16 in1 video input 1. ac-couple in1 with a series 0.1? capacitor. 18 in2 video input 2. ac-couple in2 with a series 0.1? capacitor. 20 in3 video input 3. ac-couple in3 with a series 0.1? capacitor. ?p e xp osed p ad . inter nal l y connected to gn d . d o not r oute any p c b oar d tr aces und er p ackag e. c onnect e p to the g r ound p l ane. s ee the p ow er - s up p l y byp assi ng and layout c onsi d er ati ons secti on. hdtv continuously variable anti-aliasing filters _______________________________________________________________________________________ 7
max7469/MAX7470 hdtv continuously variable anti-aliasing filters 8 ________________________________________________________________________________________ use the high level for bipolar signals, such as c (chro- ma) or p b /p r . see table 1 for more details. component/composite selection the max7469/MAX7470 accept component or com- posite inputs. when configured for composite video inputs, the color-burst filter is enabled; if configured for component video inputs, the color-burst filter is dis- abled. this filter is separate from the main filter and not in the direct signal path so that it has no effect on the overall frequency response. with normal video signals and levels, the use of this color-burst filter has a negligi- ble effect on the sync detection. it has a more signifi- cant effect under conditions of low-signal amplitude coupled with higher relative amplitude color burst. external sync detection (extsync) when filtering a video signal without embedded sync information, such as computer formats (rgbhv) with separate sync signals, use the external sync mode (see table 3) and apply the horizontal sync source to the extsync pin. the sync detector determines when the clamp circuit is turned on. the max7469/MAX7470 are able to detect positive or negative polarity external syncs with ttl logic levels. use the i 2 c interface to program the polarity of the external sync signal. filter the internal video filter delivers an optimized response with a steep transition band to achieve a wide pass- band along with excellent stopband rejection. in addi- tion, the filter is optimized to provide an excellent time domain response with low overshoot. setting the filter frequency use the i 2 c interface to vary the frequency response (-3db cutoff frequency) of the filter in the max7469/ MAX7470 from less than the sd passband to beyond the hd passband in 256 linear steps. write command byte 12h to access the frequency register, followed by an 8-bit data word that corresponds to the desired frequency. see the frequency register section for more details. the frequency set by the max7469/MAX7470 is the -3db point. set the frequency according to the desired flat passband response. optimizing the frequency response select the frequency response according to the resolution of the video-signal format. high-definition signals require higher bandwidth, while standard-definition signals require less bandwidth. the actual bandwidth contained in the video signal is a function of the visual resolution of the signal. this bandwidth is typically less than what is indicated by the format resolution (1080i, 720p, etc.). for more information, see maxim application note 750: bandwidth versus video resolution , which is available on www.maxim-ic.com. the frequency response can be optimized to improve the overall performance. it is important, at a minimum, to meet the nyquist criterion. beyond this, the frequency response can be further optimized. in oversampled sys- tems, the sample rate is significantly more than the desired passband response. the extra frequency span between the passband and the sample rate contains noise and other undesirable interferers that can be elimi- nated by setting the corner frequency of the filter to just pass the desired bandwidth. this results in a higher sig- nal-to-noise ratio of the overall system. filter bypass the max7469/MAX7470 offer selectable filter bypass- ing that allows the input video signals to bypass the internal filters and reach the output buffers unfiltered. write the appropriate command byte to enable (0eh) or disable (0fh) filter-bypass mode as shown table 3. output buffer each output buffer can drive a 2v p-p signal into a 150 video load. the max7469/MAX7470 can drive a dc- or ac-coupled load. output ac-coupling capacitors can be eliminated when driving a cable, thereby eliminating the normal adverse effects caused by these large capacitors, such as line, and field-time distortion, also known as droop. the output dc level is controlled to limit the dc voltage on the cable so that the blanking level of the video signal is always less than 1v, meeting digital tv specification. see the output considerations section for more information. gain options the max7469 features an overall gain of 0db, while the MAX7470 features an overall gain of +6db. use the MAX7470 when driving a back-matched cable and the table 1. clamp levels clamp level input signal format channel 1 channel 2 channel 3 y p b p r low high high g s br low high high cvbs y c low low high y p b p r (sync on all signals) low low low r g b h v high high high
max7469/MAX7470 hdtv continuously variable anti-aliasing filters _______________________________________________________________________________________ 9 max7469 when driving an adc or video decoder with an input range the same as the input to the max7469. for added flexibility, the max7469 accepts input signals with twice the standard video-signal range, which can be used for driving an adc or video decoder with an input signal range that accepts a larger signal swing. the MAX7470 can also be used to drive an adc or video decoder when a gain of two is desired. output clamp level the max7469/MAX7470 output can be dc- or ac- coupled. the nominal output clamp level in the dc-coupled case depends on the clamp voltage set- ting and can be determined according to table 2. as shown in the sync detector and clamp settings section, the low clamp level is used for signals with sync information and determines the voltage level of the sync tip, while the high clamp level is used for signals without sync information and sets the blanking level. the absolute voltage level of the output signal is rela- tive to the output clamp level. a video signal containing sync information (i.e., cvbs or y) is unipolar above the clamp level and conversely, a video signal without sync (i.e., p b p r or c) is bipolar around the clamp level. power-down mode the max7469/MAX7470 include a power-down mode that reduces the supply current from 180ma (typ) to 1ma (typ) by powering down the analog circuitry. the i 2 c interface remains active, allowing the device to return to full-power operation. the clamp settling time (see the electrical characteristics section) limits the wake-up time of the max7469/MAX7470. after exiting the power-down mode, the max7469/MAX7470 resume normal operation using the settings stored prior to power-down. the power-down and wake-up modes are controlled through the command byte (see table 3). a software reset sets the control/status register to its default conditions, but the frequency register is not affected. power-on reset (por) the max7469/MAX7470 include a por circuit that resets the internal registers and i 2 c interface to their default conditions (see tables 4, 5, and 6). serial interface the max7469/MAX7470 feature an i 2 c-compatible, 2-wire serial interface consisting of a bidirectional serial-data line (sda) and a serial-clock line (scl). sda and scl facilitate bidirectional communication between the max7469/ MAX7470 and the master at rates up to 400khz. the max7469/MAX7470 have a command interpreter that is accessed by writing a valid command byte. once a command byte is written to the max7469/ MAX7470, the command interpreter updates the con- trol/status register accordingly. see the control/status register section for more information. the command interpreter also controls access to the frequency regis- ter through a command byte (see the command byte ( write cycle) section). the max7469/MAX7470 are transmit/receive slave-only devices, relying upon a master to generate a clock sig- nal. the master (typically a ?) initiates data transfer on the bus and generates scl. a master device communicates to the max7469/ MAX7470 by transmitting the proper address (see the slave address section) followed by a command and/or data words. each transmit sequence is framed with a start (s) or repeated start (sr) condition and a stop (p) condition. the sda driver is an open-drain output, requiring a pullup resistor (2.4k or greater) to generate a logic- high voltage. optional resistors (24 ) in series with sda and scl protect the device inputs from high-volt- age spikes on the bus lines. series resistors also mini- mize crosstalk and undershoot of the bus signals. bit transfer each scl rising edge transfers 1 data bit. nine clock cycles are required to transfer the data into or out of the max7469/MAX7470. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high are read as control signals (see the start and stop conditions section). when the serial interface is inactive, sda and scl idle high. table 2. output clamp level clamp setting output clamp level (v) low 1.0 (typ) high 1.6 (typ)
max7469/MAX7470 hdtv continuously variable anti-aliasing filters 10 _______________________________________________________________________________________ start and stop conditions a master device initiates communication by issuing a start condition, a high-to-low transition on sda with scl high (figure 2). the master terminates transmission by a stop condition (see the acknowledge bit (ack) and not- acknowledge bit (nack) section). a stop condition is a low-to-high transition on sda while scl is high (figure 2). the stop condition frees the bus. if a repeated start condition is generated instead of a stop condition, the bus remains active. when a stop condition or incorrect address is detected, the max7469/ MAX7470 then ignore all communication on the i 2 c bus until the next start or repeated start condition, minimizing digital noise and feedthrough. early stop conditions the max7469/MAX7470 recognize a stop condition at any point during transmission except when a stop condition occurs in the same high pulse as a start condition (figure 3). this condition is not a legal i 2 c for- mat; at least one clock pulse must separate any start and stop conditions. the max7469/MAX7470 discard any data received during a data transfer aborted by an early stop condition. repeated start (s r ) conditions an sr condition is used to indicate a change in direc- tion of data flow (see the read cycle section). sr can also be used when the bus master is writing to several i 2 c devices and does not want to relinquish control of the bus. the max7469/MAX7470 serial interface sup- ports continuous write operations with (or without) an sr condition separating them. start start stop illegal stop legal stop condition illegal stop condition scl sda scl sda figure 3. early stop conditions scl sda ss r p figure 2. start/stop conditions
max7469/MAX7470 hdtv continuously variable anti-aliasing filters ______________________________________________________________________________________ 11 acknowledge bit (ack) and not-acknowledge bit (nack) successful data transfers are acknowledged with an acknowledge bit (ack) or a not-acknowledge bit (nack). both the master and the max7469/MAX7470 (slave) generate acknowledge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (figure 4). to generate a nack, the receiver allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse (ninth pulse) and leaves it high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccess- ful data transfer happens if a receiving device is busy or if a system fault has occurred. in the event of an unsuc- cessful data transfer, the master should reattempt com- munication at a later time. the max7469/MAX7470 generate an acknowledge bit when receiving an address or data by pulling sda low during the ninth clock pulse. when transmitting data during a read, the max7469/MAX7470 do not drive sda during the ninth clock pulse (i.e., the external pullups define the bus as a logic-high) so that the receiver of the data can pull sda low to acknowledge receipt of data. slave address a bus master initiates communication with a slave device by issuing a start condition, followed by the 7-bit slave address (figure 5). when idle, the max7469/MAX7470 wait for a start condition, followed by their slave address. the serial interface compares each address bit by bit, allowing the interface to power down and discon- nect from scl immediately if an incorrect address is detected. after recognizing a start condition followed by the correct address, the max7469/MAX7470 are ready to accept or send data. the least significant bit (lsb) of the address byte (r/ w ) determines whether the master is writing to or reading from the max7469/MAX7470 (r/ w = 0 selects a write condition, r/ w = 1 selects a read condition). after receiving the proper address, the max7469/MAX7470 (slave) issue an ack by pulling sda low for one clock cycle. the max7469/MAX7470 slave address consists of 5 fixed bits, a6?2 (set to 10010), followed by 2 pin-pro- grammable bits, a1 and a0. the most significant address bit (a6) is transmitted first, followed by the remaining bits. addresses a1 and a0 can also be driven dynamically if required, but the values must be stable when they are expected in the address sequence. 1 8 9 s sda scl not acknowledge acknowledge sda scl 1 0 1 0 a1 a0 0 r/w msb lsb ack . figure 4. acknowledge and not-acknowledge bits figure 5. slave-address byte definition
max7469/MAX7470 hdtv continuously variable anti-aliasing filters 12 _______________________________________________________________________________________ command byte (write cycle) a write cycle begins with the bus master issuing a start condition followed by 7 address bits (figure 5) and 1 write bit (r/ w = 0). after successfully receiving its address, the max7469/MAX7470 (slave) issue an ack. the slave recognizes the next byte after a successfully received address as the command byte (table 3). use the command byte to configure the max7469/ MAX7470. while most of the commands listed in table 3 modify the functionality of the max7469/MAX7470, some commands prepare the device for further data transfers (see the control/status register and frequency register sections). if the write cycle is pre- maturely aborted, the register is not updated, and the command byte: individual bit definitions c7 c6 c5 c4 c3 c2 c1 c0 description 00000000 enters power-down mode. 00000001 wake-up; resumes normal operation using the frequency/status previously stored (unless power has been cycled). 00000010 sets in1 clamp voltage level to low. 00000011 sets in1 clamp voltage level to high. 00000100 sets in2 clamp voltage level to low. 00000101 sets in2 clamp voltage level to high. 00000110 sets in3 clamp voltage level to low. 00000111 sets in3 clamp voltage level to high. 00001000 selects component input, color-burst filter disabled. 00001001 selects composite input, color-burst filter enabled. 00001010 selects internal sync. 00001011selects external s ync. 00001100 selects positive polarity external sync. 00001101 selects negative polarity external sync. 00001110 enables filters. 00001111 disables filters, enters bypass mode. 00010000 resets the control/status register to the default values as described in the control/ status register section. this command does not affect the frequency register. 00010001 requests a control/status register read. the interface expects an sr condition to follow with address and read/write set to read so data can be driven onto the bus. 00010010 loads the frequency register with the data byte following the command byte. 00010011 requests a frequency register read. the interface expects an sr condition to follow with address and read/write set to read so data can be driven onto the bus. table 3. command byte definition
max7469/MAX7470 hdtv continuously variable anti-aliasing filters ______________________________________________________________________________________ 13 write sequence must be repeated. figures 6 and 7 show examples of write sequences. read cycle in read mode (r/ w = 1), the max7469/MAX7470 write the contents of the control/status or frequency registers to the bus. when the command byte indicates a read operation of either the control/status or the frequency register, the serial interface expects an sr condition to follow the command byte. after sending an sr, the mas- ter sends the max7469/MAX7470 slave address byte followed by a r/ w bit (set to 1 to indicate a read). the slave device (max7469/MAX7470) generates an ack for the second address word and immediately after the ack clock pulse, the direction of data flow reverses. the slave (max7469/MAX7470) then transmits 1 byte of data containing the value of the register that was sda scl 10010a1a0 r/w c7 c6 c5 c4 c3 c2 c1 c0 ack ack out in out in to max7469/MAX7470 sda (cont) sda direction sda direction scl (cont) f7 f6 f5 f4 f3 f2 f1 ack out f0 in in start stop 0001001 0 command byte c7?0 is 0010010. sda sda direction scl 10010a1a0r/w c7 c6 c5 c0 ack ack out in out in to max7469/MAX7470 in start stop 0000000 0 c4 c3 c2 c1 the command byte is for power-down. figure 6. write sequence to update the frequency register figure 7. write sequence for a command byte
max7469/MAX7470 hdtv continuously variable anti-aliasing filters 14 _______________________________________________________________________________________ video-signal format f7 f6 f5 f4 f3 f2 f1 f0 code no. approximate frequency (-3db) mhz standard definition (interlaced) 0 0 1 0 1 0 0 0 40 10 standard definition (progressive) 0 1 0 1 1 0 1 0 90 15 high-definition low bandwidth 1 1 0 1 1 1 0 0 220 30 high-definition high bandwidth 1 1 1 1 1 1 1 1 255 34 (default) table 6. frequency register setting for different video-signal formats selected in the command byte. figure 8 shows a basic read sequence. note: the master has to write a command byte, requesting to read the control/status or frequency reg- ister, to the slave (max7469/MAX7470) before the mas- ter can read the contents of the selected register. control/status register the max7469/MAX7470 store their status in an 8-bit register that can be read back by the master. the indi- vidual bits of the control/status register are summarized in tables 4 and 5. the power-on default value of this register is 03h. frequency register the frequency response (-3db passband edge) of the max7469/MAX7470 can be continuously varied in 256 linear steps by changing the codes in the frequency reg- ister (table 6). see the command byte ( write cycle) sec- tion for a write sequence to update the frequency register. sda scl 10010a1a0 r/w c7 c6 c5 c4 c3 c2 c1 c0 ack ack out in out in to max7469/MAX7470 sda (cont) sda direction sda direction scl (cont) d7 d6 d5 d4 d3 d2 d1 d0 ack ack out in in start 1 0 0 1 0 a1 a0 r/w stop sr 0001001/0 1 figure 8. basic read sequence control/status register s7 s6 s5 s4 s3 s2 s1 s0 table 4. control/status register table 5. control/status register bit description bit description s7 0 = component input signal selected (default). 1 = composite input signal selected. s6 0 = internal sync enabled (default). 1 = external sync enabled. s5 0 = external sync: positive polarity (default). 1 = external sync: negative polarity. s4 0 = normal operation mode (default). 1 = power-down mode. s3 0 = filters enabled (default). 1 = bypass mode?o filtering. s2 0 = clamp voltage for in1 set to low (default). 1 = clamp voltage for in1 set to high. s1 0 = clamp voltage for in2 set to low. 1 = clamp voltage for in2 set to high (default). s0 0 = clamp voltage for in3 set to low. 1 = clamp voltage for in3 set to high (default).
max7469/MAX7470 hdtv continuously variable anti-aliasing filters ______________________________________________________________________________________ 15 i 2 c compatibility the max7469/MAX7470 are compatible with existing i 2 c systems supporting standard i 2 c 8-bit communica- tions. the general call address is ignored, and cbus formats are not supported. the device? address is compatible with 7-bit i 2 c addressing protocol only; 10- bit address formats are not supported. applications information input considerations use 0.1? ceramic capacitors to ac-couple the inputs. the inputs cannot be dc-coupled. the internal clamp circuit stores a dc voltage across the input capacitors to obtain the appropriate output dc voltage level. increasing the value of these capacitors to improve line- time distortion is not necessary due to the extremely low input leakage current yielding a very low line-time dis- tortion performance. the max7469/MAX7470 provide a high input imped- ance to allow a nonzero source impedance to be used, such as when the input is connected directly to a back- matched video cable, ensuring the external resistance determines the termination impedance. output considerations the max7469/MAX7470 outputs can be dc- or ac- coupled. the MAX7470, with its +6db gain, is typically connected to a 75 series back-match resistor fol- lowed by the video cable. because of the inherent divide-by-two of this configuration, the blanking level of the video signal is always less than 1v, which complies with digital tv requirements. the max7469, with its 0db gain, is typically connected to an adc or video decoder. this can be a dc or ac connection. if a dc connection is used, ensure that the dc input requirements of the adc or video decoder are compatible. if an ac connection is used, choose an ac-coupling capacitor value that ensures that the lowest frequency content in the video signal is passed and the line-time distortion is kept within desired limits. the selection of this value is a function of the input impedance and, more importantly, the input leakage of the circuit being driven. use a video clamp to reestablish the dc level, if not already included in the subsequent circuit. the outputs of the max7469/MAX7470 are fully protected against a short-circuit condition either to ground or the positive supply of the device. power-supply bypassing and layout considerations the max7469/MAX7470 operate from a single +5v ana- log supply and a +3.3v digital supply. bypass av dd to gnd with a 0.1? capacitor and an additional 1? capacitor in parallel for additional low-frequency decou- pling. determine the proper power-supply bypassing necessary by taking into account the desired distur- bance level tolerable on the output, the power-supply rejection of the max7469/MAX7470, and the amplitude and frequency of the disturbance signals present in the vicinity of the max7469/MAX7470. use an extensive ground plane to ensure optimum performance. the three av dd pins (pins 7, 9, and 11) that supply the individual channels can be connected together and bypassed as one, provided the components are close to the pins. bypass dv dd to dgnd with a 0.1? capacitor. all ground pins (gnd) must be connected to a low imped- ance ground plane as close as possible to the device. place the input termination resistors as close as possi- ble to the device. alternatively, the terminations can be placed further from the device if the pc board traces are designed to be a controlled impedance of 75 . minimize parasitic capacitance as much as possible to avoid performance degradation in the upper frequency range possible with the max7469/MAX7470. refer to the max7469/MAX7470 evaluation kit for a proven pc board layout. exposed pad and heat dissipation the max7469/MAX7470 tqfn package has an exposed pad on its bottom. this pad is electrically con- nected, internal to the device, to gnd. do not route any pc board traces under the package. the max7469/MAX7470 typically dissipate 900mw of power, therefore, pay careful attention to heat disper- sion. the use of at least a two-layer board with a good ground plane is recommended. to maximize heat dis- persion, place copper directly under the max7469/ MAX7470 package so that it matches the outline of the plastic encapsulated area. do the same thing on the bottom ground plane layer and then place as many vias as possible connecting the top and bottom layers to thermally connect it to the ground plane. maxim has evaluated a four-layer board using fr-4 material and 1oz copper with equal areas of metal on the top and bottom side coincident with the plastic encapsulated area of the 20-pin tqfn package. the two middle layers are used as power and ground
max7469/MAX7470 hdtv continuously variable anti-aliasing filters 16 _______________________________________________________________________________________ planes. the board has 21, 15-mil, plated-through via holes between the top, bottom, and ground plane lay- ers. thermocouple measurements confirm device tem- peratures to be safely within maximum limits. chip information process: bicmos typical operating circuit a/d a/d a/d decoder clamp level i 2 c interface scl sda ext sync enable in1 75 y/g 75 75 in3 in2 0db (+6db) 0db (+6db) 0db (+6db) gnd dv dd dgnd a1 a0 out3 out2 out1 av dd ext sync sync detector bypass frequency select clamp/ bias clamp/ bias clamp/ bias ( ) for MAX7470 5mhz to 34mhz programmable passband lowpass filter 5mhz to 34mhz programmable passband lowpass filter 5mhz to 34mhz programmable passband lowpass filter p b /b p r /r 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f max7469 MAX7470
max7469/MAX7470 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 17 2006 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. heslington hdtv continuously variable anti-aliasing filters qfn thin.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)

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